Conventionally, a Group III nitride semiconductor formed on a substrate has been used as a functional material for fabricating pn-junction Group III nitride semiconductor light-emitting devices which emit visible light of short wavelength such as light-emitting diodes (LEDs) and laser diodes (LDs) (see, for example, Japanese Patent Application Laid-Open (kokai) No. 2000-332364). For example, in fabrication of an LED emitting near-UV light, blue light, or green light, n-type or p-type aluminum gallium nitride (AlXGaYN, 0≦X, Y≦1, X+Y=1) is employed for forming a cladding layer (see, for example, Japanese Patent Application Laid-Open (kokai) No. 2003-229645). Similarly, gallium indium nitride (GaYInZN, 0≦Y, Z≦1, Y+Z=1) is employed for fabricating a light-emitting layer (see, for example, Japanese Patent Publication (kokoku) No. 55-3834).
Generally, in conventional Group III nitride semiconductor light-emitting devices, an n-type or a p-type Group III nitride semiconductor layer serving as a cladding layer is joined to a light-emitting layer, in order to fabricate a light-emitting member having a hetero-junction structure for attaining high emission intensity. For example, in order to fabricate a light-emitting member having a doublehetero-junction structure, the light-emitting layer is composed of a semiconductor such as GayInzN (0≦Y, Z≦1, Y+Z=1), to which an n-type or a p-type Group III nitride semiconductor layer serving as a cladding layer is joined (see, for example, a book written and edited by Isamu AKASAKI, “Group III-V Compound Semiconductors,” published Baifukan Co., Ltd., Chapter 13, May 20 (1995)).
Conventionally, an n-type Group III nitride semiconductor layer interposed between, for example, a substrate and a light-emitting layer, is usually formed from a silicon (Si)-doped Group III nitride semiconductor. In this connection, a semiconductor layer; for example, an Si-doped n-type AlXGaYN (0≦X, Y≦1, X+Y=1) layer having a resistivity controlled through modification of the amount of silicon (Si) as a dopant, is employed (see, for example, Japanese Patent No. 3383242).
However, when a large amount of silicon is added during vapor growth of a low-resistive n-type Group III nitride semiconductor layer, problematic cracks are generated in the layer. In other words, even when conventional technical means; i.e., doping with silicon, is employed, a low-resistive and continuous n-type Group III nitride semiconductor layer has not been reliably obtained.
Further, in the case where Si is used as a dopant, it is reported that highly efficient LED can be produced by stacking an n-type contact layer for n-type electrode formation onto a layer having a lower carrier concentration than the n-type contact layer (see, for example, Japanese Patent Application Laid-Open (kokai) No. 9-129920).
An LED in which Si has been doped into the n-type layer, however, has a problem that, due to the movement of Si within the semiconductor crystal by energization for a long period of time, the emission intensity is lowered after aging. Further, in some cases, a peak inverse voltage reduction phenomenon is observed. The highly efficient LED described in the above Japanese Patent No. 3383242 suffers from the same problems.
Meanwhile, in addition to silicon, germanium (Ge) is known to be an n-type impurity element (see, for example, Japanese Patent Application Laid-Open (kokai) No. 4-170397). As compared with silicon, germanium (Ge) has poor doping efficiency and, therefore, use of germanium as a dopant is disadvantageous for producing a low-resistive n-type Group III nitride semiconductor layer. When Ge is added in a high concentration so as to produce a low-resistive n-type Group III nitride semiconductor layer, pits that impair flatness of the surface of the n-type Group III nitride semiconductor layer are generated, which is problematic.
Further, in the conventional group III nitride semiconductor light-emitting device, in many cases, the substrate is a sapphire substrate. In this connection, a technique for improving light emission characteristics by two-stage growth through a buffer layer is disclosed in which the angle of the surface of the sapphire substrate to C plane (0001) is brought to 5 degrees or less (see Japanese Patent Application Laid-Open (kokai) No. 9-23026). In this Japanese Patent Application Laid-Open (kokai) No. 9-23026, however, only a technique for improving brightness in the light-emitting device (LED) is disclosed, and any technique for improving the flatness and specularity of a crystal surface, which affects a device formation process and the characteristics of a light-emitting device, is not disclosed. When the angle of inclination of the surface of the substrate is simply brought to not more than 5 degrees, as the step density of the surface of the substrate is not satisfactorily specified, the problem of nonuniform dopant distribution and the problem of lowered surface flatness cannot be solved.